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SY89464U
Precision LVPECL 1:10 Fanout with 2:1 Runt Pulse Eliminator MUX and Internal Termination
General Description
The SY89464U is a low jitter 1:10 LVPECL fanout buffer with a 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89464U's unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or "runt" pulses during switchover. In addition, a unique FailSafe Input (FSI) protection prevents metastable output conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV). The differential input includes Micrel's unique, 3-pin internal termination architecture that allows customers to interface to any differential signal (ACor DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K-compatible LVPECL with fast rise/fall times guaranteed to be less than 220ps. The SY89464U operates from a 2.5V 5% or 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89464U is part of Micrel's high-speed, Precision (R) Edge product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge
(R)
Features
* Selects between two sources, and provides 10 precision LVPECL copies * Guaranteed AC performance over temperature and supply voltage: - Wide operating frequency: 1kHz to >1.5GHz - < 1100ps In-to-Out tpd - < 220ps tr/tf * Unique, patent-pending MUX input isolation design minimizes adjacent channel crosstalk * Fail-Safe Input prevents oscillations * Ultra-low jitter design: - <1psRMS random jitter - <1psRMS cycle-to-cycle jitter - <10psPP total jitter (clock) - <0.7psRMS MUX crosstalk induced jitter * Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) * 800mV LVPECL output * 2.5V 5% or 3.3V 10% supply voltage * Output enable * -40C to +85C industrial temperature range * Available in 44-pin (7mm x 7mm) MLFTM package
Applications
* Redundant clock switchover * Fail-safe clock protection
Markets
* * * *
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
LAN/WAN Enterprise servers ATE Test and measurement
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SY89464U
Typical Application
Simplified Example Illustrating Runt Pulse Eliminator (RPE) when Primary Clock Fails
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SY89464U
Ordering Information(1)
Part Number SY89464UMG SY89464UMGTR
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals Only. 2. Tape and Reel.
(2)
Package Type MLF-44 MLF-44
Operating Range Industrial Industrial
Package Marking SY89464U with Pb-Free bar-line Indicator SY89464U with Pb-Free bar-line Indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
44-Pin MLFTM (MLF-44)
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SY89464U
Pin Description
Pin Number 2, 5 7, 10 Pin Name IN0, /IN0 IN1, /IN1 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each pin of a pair internally terminates to a VT pin through 50. Please refer to the "Input Interface Applications" section for more details. Reference Voltage: These outputs bias to VCC -1.2V. They are used for ACcoupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR capacitor to VCC. Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is 1.5mA. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. Please refer to the "Input Interface Applications" section for more details. Positive Power Supply: Bypass with 0.1F||0.01F low ESR capacitors as close to the VCC pins as possible.
4, 9
VREF-AC0 VREF-AC1
3, 8 13, 15, 22, 23, 28 33, 34, 41, 43, 44 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 42 1, 6, 11
VT0, VT1
VCC Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4 Q5, /Q5 Q6, /Q6 Q7, /Q7 Q8, /Q8 Q9, /Q9 SEL GND, Exposed Pad
Differential Outputs: These differential LVPECL outputs are a logic function of the IN0, IN1, and SEL inputs. Please refer to the "Truth Table" below for details.
This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. VTH = VCC/2. Ground: Ground and exposed pad must be connected to the same ground plane. Power-On Reset (POR) initialization capacitor. When using the multiplexer with RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in a known state. See "Power-On Reset (POR) Description" section for more details regarding capacitor selection. If this pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. The CAP pin should never be left open or tied directly to GND. Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q9 outputs. It is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. When disabled, CLK output goes LOW and /CLK goes HIGH. EN being synchronous, outputs will be enabled/disabled when they are in LOW state. Thus, a runt pulse is avoided if the device is enable/disabled by an asynchronous control. VTH = VCC/2.
12
CAP
14
EN
Truth Table
Inputs IN0 0 1 X X /IN0 1 0 X X IN1 X X 0 1 /IN1 X X 1 0 SEL 0 0 1 1 Outputs Q 0 1 0 1 /Q 1 0 1 0
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SY89464U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................ -0.5V to +4.0V Input Voltage (VIN) ....................................-0.5V to VCC LVPECL Output Current (IOUT) ...................................... Continuous .................................................... 50mA Surge ........................................................... 100mA Input Current (IIN) ........................................................... IN, /IN........................................................... 50mA VT ............................................................... 100mA VREF-AC Current Source/Sink Current on VREF-AC .................... 2mA Lead Temperature (soldering, 20 sec.)............ +260C Storage Temperature (Ts) ...................-65C to 150C
Operating Ratings(2)
Supply Voltage (VCC) ....................+2.375V to +2.625V ........................................................ +3.0V to +3.6V Ambient Temperature (TA) .................. -40C to +85C (3) Package Thermal Resistance MLFTM ( JA) Still-Air ..................................................... 24.4C/W MLFTM ( JB) Junction-to-Board ..................................... 8.1C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VT_IN VREF-AC
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. VIN (max) is specified when VT is floating.
Parameter Power Supply Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-/IN| Input Voltage Threshold that Triggers FSI IN-to-VT (IN, /IN) Output Reference Voltage
Condition
Min 2.375 3.0
Typ 2.5 3.3 120 50 100
Max 2.625 3.6 160 55 110 VCC VIH-0.1 2.5
Units V V mA V V V V
No load, max VCC 45 90 1.2 0 See Figure 1a. Note 5. See Figure 1b. 0.1 0.2
30
100 1.28
mV V V
VCC-1.3
VCC-1.2
VCC-1.1
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SY89464U
LVPECL Outputs DC Electrical Characteristics(6)
VCC = 2.5V 5% or 3.3V 10%; RL = 50 to VCC-2V; TA = -40C to + 85C, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage Q, /Q Output LOW Voltage Q, /Q Output Voltage Swing Q, /Q Differential Output Voltage Swing Q, /Q See Figure 1a. See Figure 1b. Condition Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC-0.895 VCC-1.695 mV mV Units V
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY89464U
AC Electrical Characteristics(7)
VCC = 2.5V 5% or 3.3V 10%; RL = 50 to VCC-2V; TA = -40C to + 85C, unless otherwise stated.
Symbol fMAX tpd Parameter Maximum Operating Frequency Differential Propagation Delay In-to-Q In-to-Q SEL-to-Q SEL-to-Q tpd Tempco tS EN tH EN tSKEW tJITTER Differential Propagation Delay Temperature Coefficient Set-up Time Hold Time Output-to-Output Skew Part-to-Part Skew Clock Random Jitter Cycle-to-Cycle Jitter Total Jitter Crosstalk-Induced Jitter tr, tf
Notes: 7. High-frequency AC-parameters are guaranteed by design and characterization. 8. Propagation delay is measured with input tr, tf 300ps (20% to 80%) and VIL 800mV. The propagation delay is function of the rise and fall times at IN. See "Typical Operating Characteristics" for details. 9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply. 10. Output-to-Output skew is measured between two different outputs under identical transitions. 11. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 12. Random Jitter is measured with a K28.7 character pattern, measured at 12
Condition VOUT 400mV 100mV < VIN 200mV 200mV < VIN 800mV
(8) (8)
Min 1.5 550 500 600
Typ 2.0 800 750
Max
Units GHz
1150 1100 17 1200
ps ps cycles ps fs/ C ps ps
o
RPE enabled, see Timing Diagram RPE disabled (VSEL = VCC/2)
500 Note 9 Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 Note 15 At full output swing. 70 0 650 5 25 300 1 1 10 0.7 220
EN-to-CLK CLK-to-EN
ps ps psRMS psRMS psPP psRMS ps
Output Rise/Fall Time (20% to 80%)
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SY89464U
Functional Description
RPE MUX and Fail-Safe Input The SY89464U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits: Runt-Pulse Eliminator (RPE) Circuit The RPE MUX provides a "glitchless" switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. The design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pairs, IN0 or IN1. Thus, either input pair may be defined as the primary input). If not required, the RPE function can be permanently disabled to allow the switchover between inputs to occur immediately. If the CAP pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. Fail-Safe Input (FSI) Circuit The FSI function provides protection against a selected input pair that drops below the minimum amplitude requirement. If the selected input pair drops sufficiently below the 100mV minimum singleended input amplitude limit (VIN), or 200mV differentially (VDIFF_IN), then the output will latch to the last valid clock state.
RPE and FSI Functionality The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1; the secondary (or alternate) clock is called CLK2. Due to the totally asynchronous relation of the IN and SEL signals, and an additional internal protection against metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. Refer to "Timing Diagrams" section for detailed information. Case #1: Two Normal Clocks and RPE-Enabled In this case, the frequency difference between the two running clocks, IN0 and IN1, must not be greater than 1.5:1. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz. If the SEL input changes state to select the alternate clock, the switchover from CLK1 to CLK2 will occur in three stages. * Stage 1: The output will continue to follow CLK1 for a limited number of pulses. * Stage 2: The output will remain LOW for a limited number of pulses of CLK2. * Stage 3: The output follows CLK2.
Timing Diagram 1
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SY89464U
Case #2: Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPEenabled). If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in three stages.
* Stage 1: The output will remain HIGH for a limited number of pulses of CLK2. * Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2. * Stage 3: The output will follow CLK2.
Timing Diagram 2 Note: Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period.
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SY89464U
Case #3: Input Clock Failure: Switching from a selected clock stuck Low to a valid clock (RPEenabled). If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages.
* Stage 1: The output will remain LOW for a limited number of falling edges of CLK2. * Stage 2: The output will follow CLK2.
Timing Diagram 3
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SY89464U
Case #4: Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE-enabled). If CLK1 fails to an undetermined state (e.g., amplitude falls below the 100mV (VIN) minimum single-ended input limit, or 200mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending upon the last valid state at the CLK1.
If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions. Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend upon rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for detailed information.
Timing Diagram 4
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SY89464U
Enable Output (EN) Description
The enable function is synchronous so that the outputs will be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt pulse when the device is enabled/disabled as can happen with asynchronous control. Disable Output(s): 1. EN toggles from High-to-Low 2. Output(s) follow the selected Clock input 3. Output (CLK) goes to a logic LOW level (/CLK goes to a logic HIGH), after next Highto-Low transition of the selected input. See Timing Diagram 5.
Enable Output(s): 1. EN toggles from Low-to-High. 2. Output(s) follow the selected clock after next HIGH-to-LOW transition of the selected input. See "Timing Diagram 5."
Timing Diagram 5
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SY89464U
Power-On Reset (POR) Description
The SY89464U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between VCC and the CAP pin (pin 12) controls the delay for the power-on reset function. The required capacitor value calculation is based upon the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V.
The following formula describes this relationship:
As an example, if the time required for the system power supply to power up past 2.3V is 12ms, then the required capacitor value on pin 12 would be:
C(F) 1F
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SY89464U
Typical Operating Characteristics
VCC = 3.3V, GND = 0V, tr / tf 300ps, RL = 50 to VCC-2V; TA = 25C, unless otherwise stated.
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SY89464U
Functional Characteristics
VCC = 2.5V, GND = 0V, VIN 400mVpk, tr/tf 300ps, RL = 50 to VCC-2V; TA = 25C, unless otherwise stated.
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SY89464U
Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Input and Output Stages
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified Differential Output Stage
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SY89464U
Input Interface Applications
Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled)
Figure 3d. CML Interface (AC-Coupled)
Figure 3e. LVDS Interface (DC-Coupled)
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SY89464U
PECL Output Interface Applications
PECL has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low EMI. PECL is ideal for driving 50- and 100-controlled impedance transmission lines. There are several techniques for terminating the PECL output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.
Figure 4b. Parallel Termination (3-Resistor)
Figure 4a. Parallel Termination-Thevenin Equivalent
Related Product and Support Documentation
Part Number SY89465U Function Precision LVDS Runt Pulse Eliminator 2 :1 MUX with 1:10 Fanout Buffer and Internal Termination MLF HBW Solutions
TM
Data Sheet Link www.micrel.com/product-info/products/sy89465u.shtml.
Application Note
www.amkor.com/products/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
New Products and Applications
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SY89464U
44 Lead MicroLeadFrameTM (MLF-44)
Packages Notes: 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packed before shipment. 3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Inc.
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